SN65LVCP1412 Datasheet, PDF (1/26 Pages) Texas Instruments – 14.2-GBPS Dual Channel, Dual Mode Linear Equalizer

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SN65LVCP1412
SLLSED2 – SEPTEMBER 2012
14.2-GBPS Dual Channel, Dual Mode Linear Equalizer
Check for Samples: SN65LVCP1412
FEATURES
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• Dual Channel, Uni-Directional, Multi-Rate,
Dual-Mode Linear Equalizer with Operation up
to 14.2Gbps Serial Data Rate for Backplane
and Cable Interconnects
• Linear Equalization Increases Link Margin for
Systems Implementing Decision Feedback
Equalizers (DFE)
• 18dB Analog Equalization at 7.1GHz with 1dB
Step Control for Backplane Mode or Cable
Mode
• Output Linear Dynamic Range: 1200mV
• Bandwidth: >20GHz – Typical
• Better than 15dB Return Loss at 7.1GHz
• Supports Out-of-Band (OOB) Signaling
• Low Power: Typically 75mW per Channel at
2.5V VCC
• 24-Terminal QFN (Quad Flatpack, No-Lead)
4mm x 5mm x 0.75mm; 0.5mm Terminal Pitch
• Excellent Impedance Matching to 100Ω
Differential PCB Transmission Lines
• GPIO or I²C Control
• 2.5V and 3.3V±5% Single Power Supply
• 2kV ESD (HBM)
• Flow-Through Pin-Out Provides Ease of
Routing
• Small Package Size Saves Board Space
APPLICATIONS
• High Speed Links in Telecommunication and
Data communication
• Backplane and Cable Interconnects for 10GbE,
16GFC,10G SONET, SAS, SATA, CPRI, OBSAI,
Infiniband, 10GBase-KR, and XFI/SFI
DESCRIPTION
The SN65LVCP1412 is an asynchronous, protocol-agnostic, low latency, two-channel linear equalizer optimized
for use up to 14.2Gbps and compensates for losses in backplane or active cable applications. The architecture of
SN65LVCP1412 is designed to work with an ASIC or a FPGA with digital equalization employing Decision
Feedback Equalizers (DFE). SN65LVCP1412 linear equalizer preserves the shape of the transmitted signal
ensuring optimum DFE performance. SN65LVCP1412 provides a low power solution while at the same time
extending the effectiveness of DFE.
SN65LVCP1412 is configurable via I²C or GPIO interface. Using the I²C interface of the SN65LVCP1412
enables the user to control independently the Equalization, Path Gain, and Output Dynamic Range for each
individual channel. In GPIO mode, Equalization, Path Gain, and Output Dynamic Range can be set for all
channels using the GPIO Input pins.
SN65LVCP1412 outputs can be disabled independently via I²C.
The SN65LVCP1412 operates from a single 2.5V or 3.3V power supply.
The package for the SN65LVCP1412 is a 24 pin 4mm x 5mm x 0.75mm QFN (Quad Flatpack, No-lead) lead-free
package with 0.5mm pitch, and characterized for operation from –40°C to 85°C.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated