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SN65LBC184_07 Datasheet, PDF (1/21 Pages) Texas Instruments – DIFFERENTIAL TRANSCEIVER WITH TRANSIENT VOLTAGE SUPPRESSION
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D Integrated Transient Voltage Suppression
D ESD Protection for Bus Terminals Exceeds:
± 30 kV IEC 61000-4-2, Contact Discharge
± 15 kV IEC 61000-4-2, Air-Gap Discharge
± 15 kV EIA/JEDEC Human Body Model
D Circuit Damage Protection of 400-W Peak
(Typical) Per IEC 61000-4-5
D Controlled Driver Output-Voltage Slew
Rates Allow Longer Cable Stub Lengths
D 250-kbps in Electrically Noisy
Environments
D Open-Circuit Fail-Safe Receiver Design
D 1/4 Unit Load Allows for 128 Devices
Connected on Bus
D Thermal Shutdown Protection
D Power-Up/-Down Glitch Protection
D Each Transceiver Meets or Exceeds the
Requirements of TIA/EIA-485 (RS-485) and
ISO/IEC 8482:1993(E) Standards
D Low Disabled Supply Current 300 µA Max
D Pin Compatible With SN75176
D Applications:
− Industrial Networks
− Utility Meters
− Motor Control
description
The SN75LBC184 and SN65LBC184 are differ-
ential data line transceivers in the trade-standard
footprint of the SN75176 with built-in protection
against high-energy noise transients. This feature
provides a substantial increase in reliability for
better immunity to noise transients coupled to the
data cable over most existing devices. Use of
these circuits provides a reliable low-cost
direct-coupled (with no isolation transformer) data
line interface without requiring any external
components.
The SN75LBC184 and SN65LBC184 can with-
stand overvoltage transients of 400-W peak
(typical). The conventional combination wave
called out in IEC 61000-4-5 simulates the
overvoltage transient and models a unidirectional
surge caused by overvoltages from switching and
secondary lightning transients.
SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236G − OCTOBER 1996 − REVISED MARCH 2007
SN65LBC184D (Marked as 6LB184)
SN75LBC184D (Marked as 7LB184)
SN65LBC184P (Marked as 65LBC184)
SN75LBC184P (Marked as 75LBC184)
(TOP VIEW)
R1
RE 2
DE 3
D4
8 VCC
7B
6A
5 GND
functional logic diagram (positive logic)
3
DE
D4
2
RE
1
R
6A
7B
Bus
V
± VP
± 1/2 VP
1.2 µs
t
50 µs
Figure 1. Surge Waveform — Combination Wave
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2002, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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