SN65HVD379 Datasheet, PDF (1/14 Pages) Texas Instruments – 3.3 V FULL-DUPLEX RS-485/RS-422 DRIVERS AND BALANCED RECEIVERS

SN65HVD379
www.ti.com
SLLS667A – FEBRUARY 2006 – REVISED MAY 2006
3.3 V FULL-DUPLEX RS-485/RS-422 DRIVERS AND BALANCED RECEIVERS
FEATURES
• Designed for INTERBUS Applications
• Balanced Receiver Thresholds
• 1/2 Unit-Load (up to 64 nodes on the bus)
• Bus-Pin ESD Protection 15 kV HBM
• Bus-Fault Protection of –7V to 12V
• Thermal Shutdown Protection
• Power-Up/Down Glitch-free Bus Inputs and
Outputs
• High Input Impedance with Low V_CC
• Monotonic Outputs During Power Cycling
• 5V Tolerant Inputs
APPLICATIONS
• Digital Motor Control
• Utility Meters
• Chassis-to-Chassis Interconnections
• Electronic Security Stations
• Industrial, Process, and Building Automation
• Point-of-Sale (POS) Terminals and Networks
• DTE/DCE Interfaces
DESCRIPTION
The SN65HVD379 is a differential line driver and
differential-input line receiver that operates with a
3.3-V power supply. Each driver and receiver has
separate input and output pins for full-duplex bus
communication designs. They are designed for
balanced transmission lines and interoperation with
ANSI TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11, and
ISO 8482:1993 standard-compliant devices.
These differential bus drivers and receivers are
monolithic, integrated circuits designed for full-duplex
bi-directional data communication on multipoint
bus-transmission lines at signaling rates⁽¹⁾ up to 25
Mbps. The SN65HVD379 is fully enabled with no
external enabling pins.
The 1/2 unit load receiver has a higher receiver input
resistance. This results in lower bus leakage currents
over the common-mode voltage range, and reduces
the total amount of current that an RS-485 driver is
forced to source or sink when transmitting.
The balanced differential receiver input threshold
makes the SN65HVD379 more compatible with
fieldbus requirements that define an external failsafe
structure.
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
BALANCED RECEIVER INPUT THRESHOLDS
Recevier Output High
Receiver Output Low
VID
SN65HVD379
D PACKAGE (TOP VIEW)
V_CC
1
R
2
D
3
GND
4
8
A
7
B
6
Z
5Y
2
R
3
D
8
A
7
B
5
Y
6
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated