SN65HVD10 Datasheet, PDF (1/20 Pages) Texas Instruments – 3.3V RS 485 TRANSCEIVERS

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SN65HVD10,āSN65HVD10Q,āSN75HVD10
SN65HVD11,āSN65HVD11Q,āSN75HVD11
SN65HVD12,āSN75HVD12
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
3.3ĆV RSĆ485 TRANSCEIVERS
FEATURES
D Operates With a 3.3-V Supply
D Bus-Pin ESD Protection Exceeds 16 kV HBM
D 1/8 Unit-Load Option Available (Up to 256
Nodes on the Bus)
D Optional Driver Output Transition Times for
Signaling Rates^† of 1 Mbps, 10 Mbps and
25 Mbps
D Meets or Exceeds the Requirements of ANSI
TIA/EIA-485-A
D Bus-Pin Short Circuit Protection From –7 V to
12 V
D Low-Current Standby Mode . . . 1 µA Typical
D Open-Circuit, Idle-Bus, and Shorted-Bus
Failsafe Receiver
D Thermal Shutdown Protection
D Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
D SN75176 Footprint
APPLICATIONS
D Digital Motor Control
D Utility Meters
D Chassis-to-Chassis Interconnects
D Electronic Security Stations
D Industrial Process Control
D Building Automation
D Point-of-Sale (POS) Terminals and Networks
DESCRIPTION
The SN65HVD10, SN75HVD10, SN65HVD11,
SN75HVD11, SN65HVD12, and SN75HVD12 combine a
3-state differential line driver and differential input line
receiver that operate with a single 3.3-V power supply.
They are designed for balanced transmission lines and
meet or exceed ANSI standard TIA/EIA-485-A and ISO
8482:1993. These differential bus transceivers are
monolithic integrated circuits designed for bidirectional
data communication on multipoint bus-transmission lines.
The drivers and receivers have active-high and active-low
enables respectively, that can be externally connected
together to function as direction control. Very low device
standby supply current can be achieved by disabling the
driver and the receiver.
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/ output
(I/O) bus port that is designed to offer minimum loading to
the bus whenever the driver is disabled or V_CC = 0. These
parts feature wide positive and negative common-mode
voltage ranges, making them suitable for party-line
applications.
D OR P PACKAGE
(TOP VIEW)
R
1
RE
2
DE
3
D
4
8
V_CC
7
B
6
A
5 GND
LOGIC DIAGRAM
(POSITIVE LOGIC)
1
R
2
RE
DE ³
4
D
6A
7B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
†The _{signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).}
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright  2002−2003, Texas Instruments Incorporated