SN65DSI84 Datasheet, PDF (1/37 Pages) Texas Instruments – MIPI DSI BRIDGE TO FLATLINK LVDS Single Channel DSI to Dual-Link LVDS Bridge

SN65DSI84
www.ti.com
SLLSEC2C – SEPTEMBER 2012 – REVISED DECEMBER 2012
MIPI® DSI BRIDGE TO FLATLINK™ LVDS
Single Channel DSI to Dual-Link LVDS Bridge
Check for Samples: SN65DSI84
FEATURES
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•234 Implements MIPI^® D-PHY Version 1.00.00
Physical Layer Front-End and Display Serial
Interface (DSI) Version 1.02.00
• Single Channel DSI Receiver Configurable for
One, Two, Three, or Four D-PHY Data Lanes
Per Channel Operating up to 1 Gbps Per Lane
• Supports 18 bpp and 24 bpp DSI Video
Packets with RGB666 and RGB888 Formats
• Suitable for 60 fps WUXGA 1920 x 1200
Resolution at 18 bpp and 24 bpp Color, 60 fps
1366 x 768 at 18 bpp and 24 bpp
• FlatLink™ Output Configurable for Single-Link
or Dual-Link LVDS
• Supports Single Channel DSI to Dual-Link
LVDS Operating Mode
• LVDS Output Clock Range of 25 MHz to 154
MHz in Dual-Link or Single-Link Modes
• LVDS Pixel Clock May be Sourced from Free-
Running Continuous D-PHY Clock or External
Reference Clock (REFCLK)
• 1.8 V Main V_CC Power Supply
• Low Power Features Include SHUTDOWN
Mode, Reduced LVDS Output Voltage Swing,
Common Mode, and MIPI® Ultra-Low Power
State (ULPS) Support
• LVDS Channel SWAP, LVDS PIN Order
Reverse Feature for Ease of PCB Routing
• ESD Rating ±2 kV (HBM)
• Packaged in 64-pin 5x5mm PBGA (ZQE)
• Temperature Range: -40°C to 85°C
APPLICATIONS
• Tablet PC, Notebook PC, Netbooks
• Mobile Internet Devices
DESCRIPTION
The SN65DSI84 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver front-end
configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The
bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data
stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz,
offering a Dual-Link LVDS, Single-Link LVDS interface with four data lanes per link.
The SN65DSI84 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24 bits-per-pixel.
Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS
interfaces.
Designed with industry compliant interface technology, the SN65DSI84 is compatible with a wide range of micro-
processors, and is designed with a range of power management features including low-swing LVDS outputs, and
the MIPI® defined ultra-low power state (ULPS) support.
The SN65DSI84 is implemented in a small outline 5x5mm PBGA at 0.5 mm pitch package, and operates across
a temperature range from -40ºC to 85ºC.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
2
MIPI is a registered trademark of Arasan Chip Systems, Inc.
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All other trademarks are the property of their respective owners.
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PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2012, Texas Instruments Incorporated