SN65CML100 Datasheet, PDF (1/15 Pages) Texas Instruments – 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER

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SN65CML100
SLLS547 – NOVEMBER 2002
1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER
FEATURES
D Provides Level Translation From LVDS or
LVPECL to CML, Repeating From CML to
CML
D Signaling Rates¹ up to 1.5 Gbps
D CML Compatible Output Directly Drives
Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
D Total Jitter < 70 ps
D Low 100 ps (Max) Part-To-Part Skew
D Wide Common-Mode Receiver Capability
Allows Direct Coupling of Input Signals
D 25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Common-Mode Range
D Propagation Delay Times, 800 ps Maximum
D 3.3-V Supply Operation
D Available in SOIC and MSOP Packages
APPLICATIONS
D Level Translation
D 622-MHz Central Office Clock Distribution
D High-Speed Network Routing
D Wireless Basestations
D Low Jitter Clock Repeater
FUNCTIONAL DIAGRAM
DESCRIPTION
This high-speed translator/repeater is designed for
signaling rates up to 1.5 Gbps to support various
high-speed network routing applications. The driver output
is compatible with current-mode logic (CML) levels, and
directly drives 50-Ω or 25-Ω loads connected to 1.8-V,
2.5-V, or 3.3-V nominal supplies. The capability for direct
connection to the loads may eliminate the need for
coupling capacitors. The receiver input is compatible with
LVDS (TIA/EIA–644), LVPECL, and CML signaling levels.
The receiver tolerates a wide common-mode voltage
range, and may also be directly coupled to the signal
source. The internal data path from input to output is fully
differential for low noise generation and low pulse-width
distortion.
The V_BB pin is an internally generated voltage supply to
allow operation with a single-ended LVPECL input. For
single-ended LVPECL input operation, the unused
differential input is connected to V_BB as a switching
reference voltage. When used, decouple V_BB with a
0.01-µF capacitor and limit the current sourcing or sinking
to 400 µA. When not used, V_BB should be left open.
This device is characterized for operation from –40°C to
85°C.
EYE PATTERN
VCC ⁸
A2
B
3
4 _VBB
7
Y
6Z
1.5 Gbps
223–1 PRBS
Vertical Scale = 500 mV/div
750 MHz
Horizontal Scale = 200 ps/div
VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 3.3 V, RT = 50 Ω
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
1The _{signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).}
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright  2002, Texas Instruments Incorporated