SN65555 Datasheet, PDF (1/9 Pages) Texas Instruments – ELECTROLUMINESCENT COLUMIN DRIVERS

Each Device Drives 32 Electrodes
90-V Output Voltage Swing Capability
Using Ramped Supply
15-mA Output Source and Sink Current
Capability
High-Speed Serially-Shifted Data Input
Totem-Pole Outputs
Latches on All Driver Outputs
description
The SN65555, SN75555, SN65556, and
SN75556 are monolithic BIDFET^† integrated
circuits designed to drive the column electrodes of
an electroluminescent display. The SN65556 and
SN75556 output sequence is reversed from the
SN65555 and SN75555 for ease in printed-circuit-
board layout.
The devices consist of a 32-bit shift register, 32
latches, and 32 output AND gates. Serial data is
entered into the shift register on the low-to-high
transition of CLOCK. When high, LATCH ENABLE
transfers the shift register contents to the outputs
of the 32 latches. When OUTPUT ENABLE is
high, all Q outputs are enabled. Data must be
loaded into the latches and OUTPUT ENABLE
must be high before supply voltage V_CC2 is
ramped up.
Serial data output from the shift register can be
used to cascade shift registers. This output is not
affected by LATCH ENABLE or OUTPUT
ENABLE.
The SN65555 and SN65556 are characterized for
operation from – 40 C to 85 C. The SN75555 and
SN75556 are characterized for operation from
0 C to 70 C.
SLDS031A – APRIL 1985 – REVISED APRIL 1993
SN75555 . . . N PACKAGE
(TOP VIEW)
Q17 1
Q16 2
Q15 3
Q14 4
Q13 5
Q12 6
Q11 7
Q10 8
Q9 9
Q8 10
Q7 11
Q6 ¹²
Q5 ¹³
Q4 ¹⁴
Q3 ¹⁵
Q2 ¹⁶
Q1 ¹⁷
SERIAL OUT ¹⁸
CLOCK ¹⁹
GND ²⁰
40 Q18
39 Q19
38 Q20
37 Q21
36 Q22
35 Q23
34 Q24
33 Q25
32 Q26
31 Q27
30 _Q28
29 _Q29
28 _Q30
27 _Q31
26 _Q32
25 _{OUTPUT ENABLE}
24 _{DATA IN}
23 _{LATCH ENABLE}
22 _VCC1
21 _VCC2
SN65555, SN75555 . . . FN PACKAGE
(TOP VIEW)
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Q32
NC
NC – No internal connection
† BIDFET – Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process.
Copyright 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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