SN54LVTH543 Datasheet, PDF (1/8 Pages) Texas Instruments – 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

SN54LVTH543, SN74LVTH543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS704D – AUGUST 1997 – REVISED APRIL 1999
D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D I_off and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V_CC )
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Thin Very Small-Outline (DGV) Packages,
Ceramic Chip Carriers (FK), Ceramic Flat
(W) Package, and Ceramic (JT) DIPs
description
SN54LVTH543 . . . JT OR W PACKAGE
SN74LVTH543 . . . DB, DGV, DW, OR PW PACKAGE
(TOP VIEW)
LEBA 1
OEBA 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
A8 10
CEAB 11
GND 12
24 V_CC
23 CEBA
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 B8
14 LEAB
13 OEAB
SN54LVTH543 . . . FK PACKAGE
(TOP VIEW)
4 3 2 1 28 27 26
A2 5
25 B2
A3 6
24 B3
A4 7
23 B4
NC 8
22 NC
A5 9
21 B5
A6 ₁₀
20 B6
A7 ₁₁
19 B7
12 13 14 15 16 17 18
These octal transceivers are designed specifically
for low-voltage (3.3-V) V_CC operation, but with the
capability to provide a TTL interface to a 5-V
system environment.
NC – No internal connection
The ’LVTH543 devices contain two sets of D-type latches for temporary storage of data flowing in either
direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for
each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA
inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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