SN54LVTH540 Datasheet, PDF (1/7 Pages) Texas Instruments – 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D I_off and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V_CC)
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Ceramic (J)
DIPs
SN54LVTH540, SN74LVTH540
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS681E – MARCH 1997 – REVISED APRIL 1999
SN54LVTH540 . . . J OR W PACKAGE
SN74LVTH540 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
OE1 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
GND 10
20 V_CC
19 OE2
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 Y8
SN54LVTH540 . . . FK PACKAGE
(TOP VIEW)
A3
3 2 1 20 19
4
18
Y1
A4 ₅
17 ^Y2
A5 6
16 Y3
A6 7
15 Y4
A7 8
14 Y5
9 10 11 12 13
description
These octal buffers/drivers are designed specifically for low-voltage (3.3-V) V_CC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
The ’LVTH540 devices are ideal for driving bus lines or buffer memory address registers. These devices feature
inputs and outputs on opposite sides of the package that facilitate printed circuit board layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2)
input is high, all outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V_CC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright © 1999, Texas Instruments Incorporated
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