SN54LVTH373_07 Datasheet, PDF (1/16 Pages) Texas Instruments – 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54LVTH373, SN74LVTH373
3.3ĆV ABT OCTAL TRANSPARENT DĆTYPE LATCHES
WITH 3ĆSTATE OUTPUTS
SCBS689H − MAY 1997 − REVISED OCTOBER 2003
D Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V_CC)
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D Support Unregulated Battery Operation
Down to 2.7 V
D I_off and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LVTH373 . . . J OR W PACKAGE
SN74LVTH373 . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q ⁹
GND ¹⁰
20 V_CC
19 _8Q
18 _8D
17 _7D
16 _7Q
15 _6Q
14 _6D
13 _5D
12 _5Q
11 _LE
SN54LVTH373 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
These octal latches are designed specifically for
low-voltage (3.3-V) V_CC operation, but with the
capability to provide a TTL interface to a
5-V system environment.
While the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
2D
3 2 1 20 19
4
18
8D
2Q ₅
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 13
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − DW
Tube
Tape and reel
SN74LVTH373DW
LVTH373
SN74LVTH373DWR
−40°C to 85°C
SOP − NS
SSOP − DB
Tape and reel
Tape and reel
SN74LVTH373NSR
SN74LVTH373DBR
LVTH373
LXH373
Tube
TSSOP − PW
Tape and reel
SN74LVTH373PW
LXH373
SN74LVTH373PWR
CDIP − J
Tube
SNJ54LVTH373J
SNJ54LVTH373J
−55°C to 125°C CFP − W
Tube
SNJ54LVTH373W SNJ54LVTH373W
LCCC - FK
Tube
SNJ54LVTH373FK SNJ54LVTH373FK
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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