SN54LVTH273 Datasheet, PDF (1/13 Pages) Texas Instruments – 3.3-V ABT OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

D Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V_CC )
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D Support Unregulated Battery Operation
Down To 2.7 V
D Buffered Clock and Direct-Clear Inputs
D Individual Data Input to Each Flip-Flop
SN54LVTH273 . . . J PACKAGE
SN74LVTH273 . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
SN54LVTH273, SN74LVTH273
3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOPS
WITH CLEAR
SCBS136M − MAY 1992 − REVISED OCTOBER 2003
D I_off Supports Partial-Power-Down-Mode
Operation
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LVTH273 . . . FK PACKAGE
(TOP VIEW)
CLR 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D ⁷
4D ⁸
4Q ⁹
GND ¹⁰
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 _6D
13 _5D
12 _5Q
11 _CLK
3 2 1 20 19
2D 4
18 8D
2Q 5
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 13
description/ordering information
These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) V_CC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D)
inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the
transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the
D-input signal has no effect at the output.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − DW
Tube
Tape and reel
SN74LVTH273DW
SN74LVTH273DWR
LVTH273
−40°C to 85°C
SOP − NS
SSOP − DB
Tape and reel
Tape and reel
SN74LVTH273NSR
SN74LVTH273DBR
LVTH273
LXH273
TSSOP − PW
Tube
Tape and reel
SN74LVTH273PW
SN74LVTH273PWR
LXH273
CDIP − J
−55°C to 125°C
LCCC − FK
Tube
Tube
SNJ54LVTH273J
SNJ54LVTH273FK
SNJ54LVTH273J
SNJ54LVTH273FK
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
1