SN54LVTH245A Datasheet, PDF (1/7 Pages) Texas Instruments – 3.3-V ABT OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V_CC)
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D I_off and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs
SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130P – MAY 1992 – REVISED APRIL 1999
SN54LVTH245A . . . J OR W PACKAGE
SN74LVTH245A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
DIR 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
GND ¹⁰
20 V_CC
19 OE
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 _B8
SN54LVTH245A . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
A3 4
18 B1
A4 5
17 B2
A5 6
16 B3
A6 7
15 _B4
A7 ⁸
14 _B5
9 10 11 12 13
description
These octal bus transceivers are designed specifically for low-voltage (3.3-V) V_CC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
These devices are designed for asynchronous communication between data buses. They transmit data from
the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the devices so the buses are effectively isolated.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V_CC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH245A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH245A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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