SN54LVTH241 Datasheet, PDF (1/12 Pages) Texas Instruments – 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V_CC)
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D I_off and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LVTH241, SN74LVTH241
3.3ĆV ABT OCTAL BUFFERS/DRIVERS
WITH 3ĆSTATE OUTPUTS
SCAS352K − MARCH 1994 − REVISED OCTOBER 2003
SN54LVTH241 . . . J OR W PACKAGE
SN74LVTH241 . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
1OE ₁
1A1 ₂
2Y4 3
1A2 4
2Y3 5
1A3 6
2Y2 7
1A4 8
2Y1 9
GND 10
20 ^V_CC
19 ^2OE
18 1Y1
17 2A4
16 1Y2
15 2A3
14 1Y3
13 2A2
12 1Y4
11 2A1
SN54LVTH241 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
These octal buffers / drivers are designed
specifically for low-voltage (3.3-V) V_CC operation,
with the capability to provide a TTL interface to a
5-V system environment.
The ’LVTH241 devices are organized as two 4-bit
line drivers with separate output-enable (1OE,
2OE) inputs. When 1OE is low or 2OE is high, the
devices pass noninverted data from the A inputs
to the Y outputs. When 1OE is high or 2OE is low,
the outputs are in the high-impedance state.
3 2 1 20 19
1A2 ₄
18 ^1Y1
2Y3 ₅
17 ^2A4
1A3 ₆
16 ^1Y2
2Y2 ₇
15 ^2A3
1A4 ₈
14 1Y3
9 10 11 12 13
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE MARKING
SOIC − DW
Tube
Tape and reel
SN74LVTH241DW
SN74LVTH241DWR
LVTH241
−40°C to 85°C
SOP − NS
SSOP − DB
Tape and reel
Tape and reel
SN74LVTH241NSR
SN74LVTH241DBR
LVTH241
LXH241
TSSOP − PW
Tube
Tape and reel
SN74LVTH241PW
SN74LVTH241PWR
LXH241
CDIP − J
Tube
SNJ54LVTH241J
SNJ54LVTH241J
−55°C to 125°C CFP − W
Tube
SNJ54LVTH241W
SNJ54LVTH241W
LCCC − FK
Tube
SNJ54LVTH241FK
SNJ54LVTH241FK
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright  2003, Texas Instruments Incorporated
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