SN54LVTH240 Datasheet, PDF (1/7 Pages) Texas Instruments – 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V_CC )
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D I_off and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) DIPs
SN54LVTH240, SN74LVTH240A
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679F – DECEMBER 1996 – REVISED MARCH 2000
SN54LVTH240 . . . J PACKAGE
SN74LVTH240A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
1OE ₁
1A1 ₂
2Y4 3
1A2 4
2Y3 5
1A3 6
2Y2 7
1A4 8
2Y1 9
GND 10
20 ^V_CC
19 ^2OE
18 1Y1
17 2A4
16 1Y2
15 2A3
14 1Y3
13 2A2
12 1Y4
11 2A1
SN54LVTH240 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
1A2 4
18 1Y1
2Y3 5
17 _2A4
1A3 ⁶
16 _1Y2
2Y2 ⁷
15 _2A3
1A4
8
14 _1Y3
9 10 11 12 13
description
These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) V_CC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
These devices are organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE
is low, the devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V_CC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH240 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH240A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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