SN54LVT16952 Datasheet, PDF (1/11 Pages) Texas Instruments – 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

SN54LVT16952, SN74LVT16952
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS151D – MAY 1992 – REVISED AUGUST 1996
D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
D Members of the Texas Instruments
Widebus™ Family
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V_CC)
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D Support Live Insertion
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes
PCB Layout
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54LVT16952 . . . WD PACKAGE
SN74LVT16952 . . . DGG OR DL PACKAGE
(TOP VIEW)
1OEAB 1
1CLKAB 2
1CLKENAB 3
GND 4
1A1 5
1A2 6
V_CC 7
1A3 8
1A4 9
1A5 10
GND 11
1A6 12
1A7 13
1A8 14
2A1 15
2A2 16
2A3 17
GND 18
2A4 19
2A5 20
2A6 21
V_CC 22
2A7 23
2A8 24
GND 25
2CLKENAB 26
2CLKAB 27
2OEAB 28
56 1OEBA
55 1CLKBA
54 1CLKENBA
53 GND
52 1B1
51 1B2
50 V_CC
49 1B3
48 1B4
47 1B5
46 GND
45 1B6
44 1B7
43 1B8
42 2B1
41 2B2
40 2B3
39 GND
38 2B4
37 2B5
36 2B6
35 V_CC
34 2B7
33 2B8
32 GND
31 2CLKENBA
30 2CLKBA
29 2OEBA
description
The ’LVT16952 are 16-bit registered transceivers designed for low-voltage (3.3-V) V_CC operation, but with the
capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high
transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input
is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT16952 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,
which provide twice the I/O pin count and functionality of standard small-outline packages in the same
printed-circuit-board area.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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