SN54LVT125 Datasheet, PDF (1/7 Pages) Texas Instruments – 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V_CC )
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D Support Live Insertion
D Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) DIPs
SN54LVT125, SN74LVT125
3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS
SCBS133D – MAY 1992 – REVISED JULY 1995
SN54LVT125 . . . J PACKAGE
SN74LVT125 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
1OE 1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 V_CC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
SN54LVT125 . . . FK PACKAGE
(TOP VIEW)
1Y
NC
2OE
NC
2A
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3OE
description
NC – No internal connection
These bus buffers are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The ′LVT125 feature independent line drivers with 3-state outputs. Each output is in the high-impedance state
when the associated output-enable (OE) input is high.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT125 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT125 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74LVT125 is characterized for operation from – 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
1