SN54LVCH245A Datasheet, PDF (1/9 Pages) Texas Instruments – OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

D EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
D Power Off Disables Outputs, Permitting
Live Insertion
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V_CC)
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Package,
Ceramic Chip Carriers (FK), and DIPs (J)
SN54LVCH245A, SN74LVCH245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES008F – JULY 1995 - REVISED JUNE 1998
SN54LVCH245A . . . J OR W PACKAGE
SN74LVCH245A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
DIR 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
GND ¹⁰
20 V_CC
19 OE
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
SN54LVCH245A . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
A3 4
18 B1
A4 5
17 B2
A5 6
16 B3
A6 7
15 _B4
A7 ⁸
14 _B5
9 10 11 12 13
description
The SN54LVCH245A octal bus transceiver is designed for 2.7-V to 3.6-V V_CC operation and the
SN74LVCH245A octal bus transceiver is designed for 1.65-V to 3.6-V V_CC operation.
These devices are designed for asynchronous communication between data buses. These devices transmit
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54LVCH245A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVCH245A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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