SN54LVC652A Datasheet, PDF (1/13 Pages) Texas Instruments – OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

D EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
D Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V_CC)
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW)
Packages, and Ceramic Chip Carriers (FK)
description
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
SN74LVC652A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
CLKAB ₁
SAB ₂
OEAB ₃
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
A8 11
GND 12
24 ^V_CC
23 ^CLKBA
22 ^SBA
21 OEBA
20 B1
19 B2
18 B3
17 B4
16 B5
15 B6
14 B7
13 B8
SN54LVC652A . . . FK PACKAGE
(TOP VIEW)
The SN54LVC652A octal bus transceiver and
register is designed for 2.7-V to 3.6-V V_CC
operation, and the SN74LVC652A octal bus
transceiver and register is designed for 1.65-V to
4 3 2 1 28 27 26
A1 5
25 OEBA
3.6-V V_CC operation.
A2 6
24 B1
These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
A2 7
23 B2
NC 8
22 NC
A4 9
21 B3
A5 10
20 B4
A6 11
19 B5
12 13 14 15 16 17 18
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. The circuitry used for select control
NC – No internal connection
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and
a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that are
performed with the ’LVC652A.
Data on the A or B data bus, or both, is stored in the internal D-type flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by
simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other
data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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