SN54LVC646A Datasheet, PDF (1/13 Pages) Texas Instruments – OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
D EPIC ™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
D Power Off Disables Outputs, Permitting
Live Insertion
D Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V_CC)
D ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW)
Packages, and Ceramic Chip Carriers (FK)
description
The SN54LVC646A octal bus transceiver and
register is designed for 2.7-V to 3.6-V V_CC
operation and the SN74LVC646A octal bus
transceiver and register is designed for 1.65-V to
3.6-V V_CC operation.
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on
the A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
are performed with the ’LVC646A.
SN74LVC646A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
CLKAB 1
SAB 2
DIR 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
A8 11
GND 12
24 V_CC
23 CLKBA
22 SBA
21 OE
20 B1
19 B2
18 B3
17 B4
16 B5
15 B6
14 B7
13 B8
SN54LVC646A . . . FK PACKAGE
(TOP VIEW)
4 3 2 1 28 27 26
A1 ₅
25 ^OE
A2 ₆
24 ^B1
A3 7
23 B2
NC 8
22 NC
A4 9
21 B3
A5 10
20 B4
A6 1112 _{13 14 15 16 17 1819} B5
NC – No internal connection
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port is stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one
register and B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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