SN54LV174 Datasheet, PDF (1/8 Pages) Texas Instruments – HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54LV174, SN74LV174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS192B – FEBRUARY 1993 – REVISED APRIL 1996
D EPIC ™ (Enhanced-Performance Implanted
CMOS) 2-µ Process
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC, T_A = 25°C
D ESD Protection Exceeds 2000 V Per
SN54LV174 . . . J OR W PACKAGE
SN74LV174 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
CLR 1
1Q 2
1D 3
2D 4
16 V_CC
15 6Q
14 6D
13 5D
MIL-STD-883C, Method 3015; Exceeds
2Q 5
12 5Q
200 V Using Machine Model
3D 6
11 4D
(C = 200 pF, R = 0)
3Q 7
10 4Q
D Latch-Up Performance Exceeds 250 mA
GND 8
9 CLK
Per JEDEC Standard JESD-17
D Package Options Include Plastic
SN54LV174 . . . FK PACKAGE
Small-Outline (D), Shrink Small-Outline
(TOP VIEW)
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
3 2 1 20 19
1D 4
18 6D
2D 5
17 5D
These hex D-type flip-flops are designed for 2.7-V
NC 6
16 NC
to 5.5-V V_CC operation.
2Q 7
15 5Q
The ’LV174 are monolithic positive-edge-
3D 8
14 _4D
9 10 11 12 13
triggered flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
NC – No internal connection
pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the transition time of the positive-going edge of the clock pulse. When
the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
The SN74LV174 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV174 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV174 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
CLR CLK D
OUTPUT
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright © 1996, Texas Instruments Incorporated
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