SN54LV165 Datasheet, PDF (1/8 Pages) Texas Instruments – PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
D EPIC™ (Enhanced-Performance Implanted
CMOS) 2-µ Process
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
< 2 V at V_CC, T_A = 25°C
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
SCES007B – MARCH 1995 – REVISED APRIL 1996
SN54LV165 . . . J OR W PACKAGE
SN74LV165 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
SH/LD 1
CLK 2
E3
F4
G5
H6
Q_H 7
GND 8
16 V_CC
15 CLK INH
14 D
13 C
12 B
11 A
10 SER
9 Q_H
SN54LV165 . . . FK PACKAGE
(TOP VIEW)
description
The ’LV165 parallel-load, 8-bit shift registers are
designed for 2.7-V to 5.5-V V_CC operation.
When the device is clocked, data is shifted toward
the serial output Q_H. Parallel-in access to each
stage is provided by eight individual direct data
inputs that are enabled by a low level at the SH/ LD
input. The ’LV165 feature a clock inhibit function
and a complemented serial output Q_H.
3 2 1 20 19
E⁴
18 D
F⁵
17 C
NC ⁶
16 NC
G⁷
15 B
H
8
14
9 10 11 12 13
A
Clocking is accomplished by a low-to-high
transition of the clock (CLK) input while SH/ LD is
NC – No internal connection
held high and clock inhibit (CLK INH) is held low. The functions of the CLK and CLK INH inputs are
interchangeable. Since a low CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLK
INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/ LD is held
high. The parallel inputs to the register are enabled while SH/ LD is held low independently of the levels of CLK,
CLK INH, or SER.
The SN54LV165 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV165 is characterized for operation from –40°C to 85°C.
SH/ LD
L
H
H
H
H
FUNCTION TABLE
INPUTS
OPERATION
CLK CLK INH
X
X
Parallel load
H
X
X
H
L
↑
Q0
Q0
Shift
↑
L
Shift
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright © 1996, Texas Instruments Incorporated
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