SN54LV123A Datasheet, PDF (1/23 Pages) Texas Instruments – DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS

SN54LV123A, SN74LV123A
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
WITH SCHMITTĆTRIGGER INPUTS
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
D 2-V to 5.5-V V_CC Operation
D Max t_pd of 11 ns at 5 V
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 3.3 V, T_A = 25°C
D Support Mixed-Mode Voltage Operation on
All Ports
D Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
D Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
D I_off Supports Partial-Power-Down Mode
Operation
D Retriggerable for Very Long Output Pulses,
up to 100% Duty Cycle
D Overriding Clear Terminates Output Pulse
D Glitch-Free Power-Up Reset on Outputs
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LV123A . . . J OR W PACKAGE
SN74LV123A . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
SN74LV123A . . . RGY PACKAGE
(TOP VIEW)
SN54LV123A . . . FK PACKAGE
(TOP VIEW)
1A ₁
1B 2
1CLR 3
1Q 4
2Q 5
2C_ext 6
2R_ext/C_ext 7
GND 8
16 ^V_CC
15 1R_ext/C_ext
14 1C_ext
13 1Q
12 2Q
11 2CLR
10 2B
9 2A
1
1B 2
1CLR 3
1Q 4
2Q 5
2C_ext 6
2R_ext/C_ext 7
8
16
15 1R_ext/C_ext
14 1C_ext
13 1Q
12 2Q
11 2CLR
10 2B
9
1CLR
1Q
NC
2Q
2C_ext
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
1C_ext
1Q
NC
2Q
2CLR
description/ordering information
NC − No internal connection
The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V V_CC operation.
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method,
the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low.
In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between C_ext and R_ext/C_ext (positive) and an external resistor
connected between R_ext/C_ext and V_CC. To obtain variable pulse durations, connect an external variable
resistance between R_ext/C_ext and V_CC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. The input/output timing diagram
illustrates pulse control by retriggering the inputs and early clearing.
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DATA information current as of publication date. Products conform to
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Production processing does not necessarily include testing of all
parameters.
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