SN54HC03 Datasheet, PDF (1/4 Pages) Texas Instruments – QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-DRAIN OUTPUTS

SN54HC03, SN74HC03
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
WITH OPEN-DRAIN OUTPUTS
SCLS077B – MARCH 1984 – REVISED MAY 1997
D Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These devices contain four independent 2-input
NAND gates. They perform the Boolean function
Y = A • B or Y = A + B in positive logic. The
open-drain outputs require pullup resistors to
perform correctly. They may be connected to
other open-drain outputs to implement active-low
wired-OR or active-high wired-AND functions.
SN54HC03 . . . J OR W PACKAGE
SN74HC03 . . . D OR N PACKAGE
(TOP VIEW)
1A ₁
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 ^V_CC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
SN54HC03 . . . FK PACKAGE
(TOP VIEW)
The SN54HC03 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC03 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
1Y
3 2 1 20 19
4
18
4A
NC 5
17 NC
2A 6
16 4Y
NC 7
15 NC
2B 8
14 3B
9 10 11 12 13
NC – No internal connection
logic symbol^†
1
1A
2
1B
&
3
1Y
4
2A
5
2B
6
2Y
9
3A
10
3B
8
3Y
12
4A
13
4B
11
4Y
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.}
Pin numbers shown are for the D, J, N, and W packages.
logic diagram (positive logic)
A
Y
B
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1997, Texas Instruments Incorporated
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