SN54GTL16616 Datasheet, PDF (1/11 Pages) Texas Instruments – 17-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS

SN54GTL16616, SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999
D Members of the Texas Instruments
Widebus ™ Family
D Universal Bus Transceiver (UBT ™)
SN54GTL16616 . . . WD PACKAGE
SN74GTL16616 . . . DGG OR DL PACKAGE
(TOP VIEW)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
D GTL Buffered CLKAB Signal (CLKOUT)
D Translate Between GTL/GTL+ Signal Levels
OEAB 1
LEAB 2
A1 3
GND 4
A2 5
56 CEAB
55 CLKAB
54 B1
53 GND
52 B2
and LVTTL Logic Levels
A3 6
51 B3
D Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
D Equivalent to ’16601 Function
D I_off Supports Partial-Power-Down Mode
Operation
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors on A Port
D Latch-Up Performance Exceeds 100 mA Per
V_CC (3.3 V) 7
A4 8
A5 9
A6 10
GND 11
A7 12
A8 13
A9 14
A10 15
A11 16
50 V_CC (5 V)
49 B4
48 B5
47 B6
46 GND
45 B7
44 B8
43 B9
42 B10
41 B11
JESD 78, Class II
A12 17 40 B12
D Distributed V_CC and GND-Pin Configuration
Minimizes High-Speed Switching Noise
D Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Ceramic Flat
(WD) Packages
GND 18
A13 19
A14 20
A15 21
V_CC (3.3 V) 22
A16 23
A17 24
39 GND
38 B13
37 B14
36 B15
35 V_REF
34 B16
33 B17
description
The ’GTL16616 devices are 17-bit universal
bus transceivers (UBTs) that provide
LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL
GND 25
CLKIN 26
OEBA 27
LEBA 28
32 GND
31 CLKOUT
30 CLKBA
29 CEBA
signal-level translation. They combine D-type
flip-flops and D-type latches to allow for transparent, latched, clocked, and clocked-enabled modes of data
transfer identical to the ’16601 function. Additionally, they provide for a copy of CLKAB at GTL/GTL+ signal
levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic levels (CLKIN). The devices provide an
interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels.
Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and
output edge control (OEC™).
The user has the flexibility of using this device at either GTL (V_TT = 1.2 V and V_REF = 0.8 V) or the preferred
higher noise margin GTL+ (V_TT = 1.5 V and V_REF = 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. V_REF is the reference input voltage for the B port. V_CC (5 V) supplies the internal and GTL circuitry while
V_CC (3.3 V) supplies the LVTTL output buffers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, OEC, and UBT are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright © 1999, Texas Instruments Incorporated
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