SN54F175 Datasheet, PDF (1/5 Pages) Texas Instruments – QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

• Contain Four Flip-Flops With Double-Rail
Outputs
• Buffered Clock and Direct Clear Inputs
• Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These monolithic, positive-edge-triggered flip-
flops utilize TTL circuitry to implement D-type
flip-flop logic with a direct clear (CLR) input.
Information at the data (D) inputs meeting setup
time requirements is transferred to outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the clock (CLK) input
is at either the high or low level, the D-input signal
has no effect at the output.
The SN54F175 is characterized for operation over
the full military temperature range of – 55°C to
125°C. The SN74F175 is characterized for
operation from 0°C to 70°C.
SN54F175, SN74F175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993
SN54F175 . . . J PACKAGE
SN74F175 . . . D OR N PACKAGE
(TOP VIEW)
CLR 1
1Q 2
1Q 3
1D 4
2D 5
2Q 6
2Q 7
GND 8
16 V_CC
15 4Q
14 4Q
13 4D
12 3D
11 3Q
10 3Q
9 CLK
SN54F175 . . . FK PACKAGE
(TOP VIEW)
1Q
3 2 1 20 19
4
18
4Q
1D ₅
17 ^4D
NC 6
16 NC
2D 7
15 3D
2Q 8
14 3Q
9 10 11 12 13
NC – No internal connection
FUNCTION TABLE
INPUTS
CLR CLK D
L
X
X
H
↑
H
H
↑
L
H
L
X
OUTPUTS
Q
Q
L
H
H
L
L
H
Q0 Q0
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1993, Texas Instruments Incorporated
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