SN54F00 Datasheet, PDF (1/13 Pages) Texas Instruments – QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54F00, SN74F00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These devices contain four independent 2-input
NAND gates. They perform the Boolean functions
Y = A • B or Y = A + B in positive logic.
The SN54F00 is characterized for operation over
the full military temperature range of – 55°C to
125°C. The SN74F00 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
(each gate)
INPUTS
A
B
H
H
L
X
X
L
OUTPUT
Y
L
H
H
logic symbol^†
1
1A
&
3
2
1Y
1B
4
2A
6
5
2Y
2B
9
3A
8
10
3Y
3B
12
4A
11
13
4Y
4B
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984 and}
IEC Publication 617-12.
logic diagram (positive logic)
1
1A
2
1B
4
2A
5
2B
9
3A
10
3B
12
4A
13
4B
Pin numbers shown are for the D, J, and N packages.
SDFS035A – MARCH 1987 – REVISED OCTOBER 1993
SN54F00 . . . J PACKAGE
SN74F00 . . . D OR N PACKAGE
(TOP VIEW)
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 V_CC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
SN54F00 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
1Y 4
18 4A
NC 5
17 NC
2A 6
16 4Y
NC 7
15 _NC
2B ⁸
14 _3B
9 10 11 12 13
NC – No internal connection
3
1Y
6
2Y
8
3Y
11
4Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1993, Texas Instruments Incorporated
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