SN54AS885_07 Datasheet, PDF (1/18 Pages) Texas Instruments – 8-BIT MAGNITUDE COMPARATORS

SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
• Latchable P-Input Ports With Power-Up
Clear
• Choice of Logical or Arithmetic
(Two’s Complement) Comparison
• Data and PLE Inputs Utilize pnp Input
Transistors to Reduce dc Loading Effects
• Approximately 35% Improvement in
ac Performance Over Schottky TTL While
Performing More Functions
• Cascadable to n Bits While Maintaining
High Performance
• 10% Less Power Than STTL for an 8-Bit
Comparison
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
description
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
SN54AS885 . . . JT PACKAGE
SN74AS885 . . . DW OR NT PACKAGE
(TOP VIEW)
L/A 1
P < QIN 2
P > QIN 3
Q7 4
Q6 5
Q5 6
Q4 7
Q3 8
Q2 9
Q1 10
Q0 11
GND 12
24 V_CC
23 PLE
22 P7
21 P6
20 P5
19 P4
18 P3
17 P2
16 P1
15 P0
14 P < QOUT
13 P > QOUT
SN54AS885 . . . FK PACKAGE
(TOP VIEW)
These advanced Schottky devices are capable of
performing high-speed arithmetic or logic
comparisons on two 8-bit binary or two’s
complement words. Two fully decoded decisions
about words P and Q are externally available at
two outputs. These devices are fully expandable
to any number of bits without external gates. To
compare words of longer lengths, the P > QOUT
and P < QOUT outputs of a stage handling less
significant bits can be connected to the P > QIN
and P < QIN inputs of the next stage handling
4 3 2 1 28 27 26
Q7 5
25 P6
Q6 6
24 P5
Q5 7
23 P4
NC 8
22 NC
Q4 ₉
21 P3
Q3 ₁₀
20 P2
Q2 ₁₁
19 P1
12 13 14 15 16 17 18
more significant bits. The cascading paths are
implemented with only a two-gate-level delay to
reduce overall comparison times for long words.
Two alternative methods of cascading are shown
in application information.
The latch is transparent when P latch-enable
NC – No internal connection
(PLE) input is high; the P-input port is latched
when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry
is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE,
P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically
– 0.25 mA, which minimizes dc loading effects.
The SN54AS885 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74AS885 is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1995, Texas Instruments Incorporated
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