SN54AS286 Datasheet, PDF (1/8 Pages) Texas Instruments – 9-BIT PARITY GENERATORS/CHECKERS WITH BUS-DRIVER PARITY I/O PORT

• Generate Either Odd or Even Parity for
Nine Data Lines
• Cascadable for n-Bit Parity
• Direct Bus Connection for Parity
Generation or Checking by Using the
Parity I/O Port
• Glitch-Free Bus During Power Up/Down
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
SN54AS286, SN74AS286
9-BIT PARITY GENERATORS/CHECKERS
WITH BUS-DRIVER PARITY I/O PORT
SDAS050B – DECEMBER 1983 – REVISED DECEMBER 1994
SN54AS286 . . . J PACKAGE
SN74AS286 . . . D OR N PACKAGE
(TOP VIEW)
G1
H2
XMIT 3
I4
PARITY ERROR 5
PARITY I/O 6
GND 7
14 V_CC
13 F
12 E
11 D
10 C
9B
8A
description
SN54AS286 . . . FK PACKAGE
(TOP VIEW)
The SN54AS286 and SN74AS286 universal 9-bit
parity generators/checkers feature a local output
for parity checking and a 48-mA bus-driving
parity input/output (I/O) port for parity
generation/checking. The word-length capability
is easily expanded by cascading.
The transmit (XMIT) control input is implemented
specifically to accommodate cascading. When
XMIT is low, the parity tree is disabled and
PARITY ERROR remains at a high logic level
regardless of the input levels. When XMIT is high,
the parity tree is enabled. PARITY ERROR
indicates a parity error when either an even
number of inputs ( A– I ) are high and PARITY I/O
is forced to a low logic level, or when an odd
number of inputs are high and PARITY I/O is
forced to a high logic level.
XMIT
NC
I
NC
PARITY ERROR
3 2 1 20 19
4
18
E
5
17 ^NC
6
16 D
7
15 NC
8
14 C
9 10 11 12 13
NC – No internal connection
The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up
or power down to prevent bus glitches.
The SN54AS286 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74AS286 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
NUMBER OF INPUTS
(A – I) THAT
ARE HIGH
PARITY
XMIT
I/O
0, 2, 4, 6, 8
l
H
1, 3, 5, 7, 9
l
L
0, 2, 4, 6, 8
h
h
h
l
1, 3, 5, 7, 9
h
h
h
l
h = high input level
H = high output level
l = low input level
L = low output level
PARITY
ERROR
H
H
H
L
L
H
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1994, Texas Instruments Incorporated
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