SN54ALVTH16501 Datasheet, PDF (1/11 Pages) Texas Instruments – 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN54ALVTH16501, SN74ALVTH16501
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES071D – JUNE 1996 – REVISED JANUARY 1999
D UBT ™ (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
D State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus ™ Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V_CC )
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D High Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V_CC)
D Power Off Disables Outputs, Permitting
Live Insertion
D High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
D Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
D Auto3-State Eliminates Bus Current
Loading When Output Exceeds V_CC + 0.5 V
D Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
SN54ALVTH16501 . . . WD PACKAGE
SN74ALVTH16501 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
OEAB 1
LEAB 2
A1 3
GND 4
A2 5
A3 6
V_CC 7
A4 8
A5 9
A6 10
GND 11
A7 12
A8 13
A9 14
A10 15
A11 16
A12 17
GND 18
A13 19
A14 20
A15 21
V_CC 22
A16 23
A17 24
GND 25
A18 26
OEBA 27
LEBA 28
56 GND
55 CLKAB
54 B1
53 GND
52 B2
51 B3
50 V_CC
49 B4
48 B5
47 B6
46 GND
45 B7
44 B8
43 B9
42 B10
41 B11
40 B12
39 GND
38 B13
37 B14
36 B15
35 V_CC
34 B16
33 B17
32 GND
31 B18
30 CLKBA
29 GND
description
The ’ALVTH16501 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V V_CC operation, but
with the capability to provide a TTL interface to a 5-V system environment.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the
B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UBT and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright © 1999, Texas Instruments Incorporated
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