SN54ALVTH16374_08 Datasheet, PDF (1/21 Pages) Texas Instruments – 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54ALVTH16374, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES068G – JUNE 1996 – REVISED NOVEMBER 2006
FEATURES
• State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus™ Design for 2.5-V
and 3.3-V Operation and Low Static Power
Dissipation
• Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With 2.3-V to
3.6-V V_CC)
• Typical V_OLP (Output Ground Bounce) <0.8 V
at V_CC = 3.3 V, T_A = 25°C
• High Drive (–24/24 mA at 2.5-V V_CC and –32/64
mA at 3.3-V )
• Power Off Disables Outputs, Permitting Live
Insertion
• High-Impedance State During Power Up and
Power Down Prevents Driver Conflict
• Uses Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to Prevent
the Bus From Floating
• Auto3-State Eliminates Bus Current Loading
When Output Exceeds V_CC + 0.5 V
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection
– Exceeds 2000 V Per MIL-STD-883, Method
3015
– Exceeds 200 V Using Machine Model
– Exceeds 1000 V Using Charged-Device
Model, Robotic Method
• Flow-Through Architecture Facilitates Printed
Circuit Board Layout
• Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
• Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink Small-Outline
(DGG), Thin Very Small-Outline (DGV)
Packages, and 380-mil Fine-Pitch Ceramic Flat
(WD) Package
SN54ALVTH16374...WD PACKAGE
SN74ALVTH16374...DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE 1
1Q1 2
1Q2 3
GND 4
1Q3 5
1Q4 6
V7
CC
1Q5 8
1Q6 9
GND 10
1Q7 11
1Q8 12
2Q1 13
2Q2 14
GND 15
2Q3 16
2Q4 17
V 18
CC
2Q5 19
2Q6 20
GND 21
2Q7 22
2Q8 23
2OE 24
48 1CLK
47 1D1
46 1D2
45 GND
44 1D3
43 1D4
42 V
CC
41 1D5
40 1D6
39 GND
38 1D7
37 1D8
36 2D1
35 2D2
34 GND
33 2D3
32 2D4
31 V
CC
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2CLK
DESCRIPTION/ORDERING INFORMATION
The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or
3.3-V V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment. These
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK), the flip-flops store the logic levels set up at the data (D) inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1996–2006, Texas Instruments Incorporated