SN54ALVTH16373 Datasheet, PDF (1/10 Pages) Texas Instruments – 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54ALVTH16373, SN74ALVTH16373
2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCES067F – JUNE 1996 – REVISED JANUARY 1999
D State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus ™ Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V_CC )
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D High Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V_CC)
D Power Off Disables Outputs, Permitting
Live Insertion
D High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
D Uses Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
D Auto3-State Eliminates Bus Current
Loading When Output Exceeds V_CC + 0.5 V
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model; and Exceeds 1000 V
Using Charged-Device Model, Robotic
Method
D Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
SN54ALVTH16373 . . . WD PACKAGE
SN74ALVTH16373 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE ₁
1Q1 ₂
1Q2 ₃
GND ₄
1Q3 ₅
1Q4 ₆
V_{CC 7}
1Q5 ₈
1Q6 ₉
GND ₁₀
1Q7 ₁₁
1Q8 ₁₂
2Q1 ₁₃
2Q2 ₁₄
GND ₁₅
2Q3 ₁₆
2Q4 ₁₇
V_{CC 18}
2Q5 ₁₉
2Q6 ₂₀
GND ₂₁
2Q7 ₂₂
2Q8 23
2OE ₂₄
48 ^1LE
47 ^1D1
46 ^1D2
45 ^GND
44 ^1D3
43 ^1D4
42 ^V_CC
41 ^1D5
40 ^1D6
39 ^GND
38 ^1D7
37 ^1D8
36 ^2D1
35 ^2D2
34 ^GND
33 ^2D3
32 ^2D4
31 ^V_CC
30 ^2D5
29 ^2D6
28 ^GND
27 ^2D7
26 ^2D8
25 ^2LE
description
The ’ALVTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for 2.5-V or 3.3-V
V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices
are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working
registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright © 1999, Texas Instruments Incorporated
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