SN54ALS652 Datasheet, PDF (1/22 Pages) Texas Instruments – OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
D Bus Transceivers/Registers
D Independent Registers and Enables for A
and B Buses
D Multiplexed Real-Time and Stored Data
D Choice of True or Inverting Data Paths
D Choice of 3-State or Open-Collector
Outputs to A Bus
D Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
DEVICE
SN74ALS651A,
’AS651
A OUTPUT
3 State
B OUTPUT LOGIC
3 State Inverting
SN54ALS’, SN54AS’ . . . JT PACKAGE
SN74ALS’, SN74AS’ . . . DW OR NT PACKAGE
(TOP VIEW)
CLKAB ₁
SAB ₂
OEAB 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
A8 11
GND 12
24 ^V_CC
23 ^CLKBA
22 SBA
21 OEBA
20 B1
19 B2
18 B3
17 B4
16 B5
15 B6
14 B7
13 B8
SN54ALS652,
SN74ALS652A,
’AS652
3 State
3 State
True
SN54ALS’, SN54AS’ . . . FK PACKAGE
(TOP VIEW)
’ALS653
Open Collector 3 State Inverting
SN74ALS654
Open Collector 3 State
True
description
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select real-time or stored data transfer. The
4 3 2 1 28 27 26
A1 ⁵
25 OEBA
A2 ⁶
24 B1
A3 7
23 B2
NC 8
22 NC
A4 9
21 B3
A5 10
20 B4
A6 11
19 B5
12 13 14 15 16 17 18
circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time
data. A low input level selects real-time data, and
NC – No internal connection
a high input level selects stored data. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the octal bus
transceivers and registers.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When
SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.
When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1996, Texas Instruments Incorporated
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