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SN54ALS534A Datasheet, PDF (1/7 Pages) Texas Instruments – OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54ALS534A, SN74ALS534A, SN74AS534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JULY 1996
D 3-State Bus Driving Inverting Outputs
D Buffered Control Inputs
D Package Options Include Plastic
Small-Outline (DW), Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) 300-mil DIPs
description
These octal D-type edge-triggered flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively low-
impedance loads. They are particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input,
the Q outputs are set to the complement of the
logic states set up at the data (D) inputs. The
’ALS534A and SN74AS534 have inverted out-
puts, but otherwise are functionally equivalent to
the ’ALS374A and SN74AS374.
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
SN54ALS534A . . . J PACKAGE
SN74ALS534A, SN74AS534 . . . DW OR N PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
SN54ALS534A . . . FK PACKAGE
(TOP VIEW)
2D
3 2 1 20 19
4
18
8D
2Q 5
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 13
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are off.
The SN54ALS534A is characterized for operation over the full military temperature range of – 55°C to 125°C.
The SN74ALS534A and SN74AS534 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE CLK D
OUTPUT
Q
L
↑
H
L
L
↑
L
H
L H or L X
Q0
H
X
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1996, Texas Instruments Incorporated
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