SN54ALS273 Datasheet, PDF (1/6 Pages) Texas Instruments – OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

• Contain Eight Flip-Flops With Single-Rail
Outputs
• Buffered Clock and Direct-Clear Inputs
• Individual Data Input to Each Flip-Flop
• Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
These octal positive-edge-triggered flip-flops
utilize TTL circuitry to implement D-type flip-flop
logic with a direct-clear (CLR) input.
Information at the data (D) inputs meeting the
setup-time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going pulse. When
CLK is at either the high or low level, the D input
signal has no effect at the output.
The SN54ALS273 is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The SN74ALS273 is characterized for
operation from 0°C to 70°C.
SN54ALS273, SN74ALS273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SDAS218A – APRIL 1982 – REVISED DECEMBER 1994
SN54ALS273 . . . J PACKAGE
SN74ALS273 . . . DW OR N PACKAGE
(TOP VIEW)
CLR 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
SN54ALS273 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
2D 4
18 8D
2Q 5
17 7D
3Q 6
16 _7Q
3D ⁷
15 _6Q
4D ⁸
14 _6D
9 10 11 12 13
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR CLK D
OUTPUT
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H H or L X
Q0
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1994, Texas Instruments Incorporated
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