SN54ALS193A Datasheet, PDF(1/8 Page) Texas Instruments – SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR

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SN54ALS193A Datasheet, PDF (1/8 Pages) Texas Instruments – SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR

SN54ALS193A, SN74ALS193A

SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

WITH DUAL CLOCK AND CLEAR

SDAS211C â DECEMBER 1982 â REVISED JULY 1996

D Look-Ahead Circuitry Enhances Cascaded

Counters

D Fully Synchronous in Count Modes

D Parallel Asynchronous Load for Modulo-N

Count Lengths

D Asynchronous Clear

D Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

description

SN54ALS193A . . . J PACKAGE

SN74ALS193A . . . D OR N PACKAGE

(TOP VIEW)

QB 2

QA 3

DOWN 4

UP 5

QC 6

QD 7

GND 8

16 VCC

15 A

14 CLR

13 BO

12 CO

11 LOAD

10 C

The âALS193A are synchronous, reversible, 4-bit

up/down binary counters. Synchronous counting

operation is provided by having all flip-flops

clocked simultaneously so that the outputs

change coincident with each other when

instructed by the steering logic. This mode of

operation eliminates the output counting spikes

normally associated with asynchronous (ripple-

clock) counters.

The outputs of the four flip-flops are triggered on

a low-to-high-level transition of either count/clock

(UP or DOWN) input. The direction of the count is

determined by which count input is pulsed while

the other count input is high.

SN54ALS193A . . . FK PACKAGE

(TOP VIEW)

DOWN

3 2 1 20 19

9 10 11 12 13

CLR

LOAD

NC â No internal connection

All four counters are fully programmable; that is, each output may be preset to either level by placing a low on

the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the

data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers

by simply modifying the count length with the preset inputs.

A high level applied to the clear (CLR) input forces all outputs to the low level. The clear function is independent

of the count and LOAD inputs. The UP, DOWN, and LOAD inputs are buffered to lower the drive requirement,

which significantly reduces the loading on, or current required by, clock drivers, etc., for long parallel words.

These counters are designed to be cascaded without the need for external circuitry. The borrow (BO) output

produces a low-level pulse while the count is zero (all Q outputs low) and the DOWN input is low. Similarily, the

carry (CO) output produces a low-level pulse while the count is 9 or 15 (all Q outputs high) and the UP input

is low. The counters can then be easily cascaded by feeding BO and CO to the count-down and count-up inputs,

respectively, of the succeeding counter.

The SN54ALS193A is characterized for operation over the full military temperature range of â 55Â°C to 125Â°C.

The SN74ALS193A is characterized for operation from 0Â°C to 70Â°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

â¢ POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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