SN54ALS161B Datasheet, PDF (1/14 Pages) Texas Instruments – SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
• Internal Look-Ahead Circuitry for Fast
Counting
• Carry Output for n-Bit Cascading
• Synchronous Counting
• Synchronously Programmable
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These synchronous, presettable, 4-bit decade
and binary counters feature an internal carry
look-ahead circuitry for application in high-speed
counting designs. The SN54ALS162B is a 4-bit
decade counter. The ′ALS161B, ′ALS163B,
′AS161, and ′AS163 are 4-bit binary counters.
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincidentally with each other
when instructed by the count-enable (ENP, ENT)
inputs and internal gating. This mode of operation
eliminates the output counting spikes normally
associated with asynchronous (ripple-clock)
counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of
the clock input waveform.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,
SN54AS163 . . . J PACKAGE
SN74ALS161B, SN74ALS163B, SN74AS161,
SN74AS163 . . . D OR N PACKAGE
(TOP VIEW)
CLR 1
CLK 2
A3
B4
C5
D6
ENP 7
GND 8
16 V_CC
15 RCO
14 Q_A
13 Q_B
12 Q_C
11 Q_D
10 ENT
9 LOAD
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,
SN54AS163 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
A4
18 Q_A
B5
17 Q_B
NC 6
16 NC
C7
15 Q_C
D
8
14
9 10 11 12 13
Q_D
These counters are fully programmable; they may
be preset to any number between 0 and 9 or 15.
Because presetting is synchronous, setting up a
low level at the load (LOAD) input disables the
counter and causes the outputs to agree with the
setup data after the next clock pulse, regardless of
the levels of the enable inputs.
NC – No internal connection
The clear function for the ′ALS161B and ′AS161 is asynchronous. A low level at the clear (CLR) input sets all
four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear function
for the SN54ALS162B, ′ALS163B, and ′AS163 is synchronous, and a low level at CLR sets all four of the flip-flop
outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The
active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to
0000 ( LLLL ).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this
function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,
produces a high-level pulse while the count is maximum (9 or 15 with Q_A high). The high-level overflow
ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed,
regardless of the level of CLK.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1994, Texas Instruments Incorporated
1