SN54AHCT16373_08 Datasheet, PDF (1/13 Pages) Texas Instruments – 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54AHCT16373, SN74AHCT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS336H – MARCH 1996 – REVISED JANUARY 2000
D Members of the Texas Instruments
Widebus ™ Family
D EPIC ™ (Enhanced-Performance Implanted
CMOS) Process
D Inputs Are TTL-Voltage Compatible
D Distributed V_CC and GND Pins Minimize
High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’AHCT16373 devices are 16-bit transparent
D-type latches with 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
SN54AHCT16373 . . . WD PACKAGE
SN74AHCT16373 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE ₁
1Q1 ₂
1Q2 ₃
GND ₄
1Q3 ₅
1Q4 ₆
V_{CC 7}
1Q5 ₈
1Q6 ₉
GND ₁₀
1Q7 ₁₁
1Q8 ₁₂
2Q1 ₁₃
2Q2 ₁₄
GND ₁₅
2Q3 ₁₆
2Q4 ₁₇
V_{CC 18}
2Q5 ₁₉
2Q6 ₂₀
GND ₂₁
2Q7 ₂₂
2Q8 23
2OE 24
48 ^1LE
47 ^1D1
46 ^1D2
45 ^GND
44 ^1D3
43 ^1D4
42 ^V_CC
41 ^1D5
40 ^1D6
39 ^GND
38 ^1D7
37 ^1D8
36 ^2D1
35 ^2D2
34 ^GND
33 ^2D3
32 ^2D4
31 ^V_CC
30 ^2D5
29 ^2D6
28 ^GND
27 ^2D7
26 2D8
25 2LE
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHCT16373 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT16373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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