SN54AH573 Datasheet, PDF (1/18 Pages) Texas Instruments – OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54AHC573, SN74AHC573
OCTAL TRANSPARENT DĆTYPE LATCHES
WITH 3ĆSTATE OUTPUTS
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004
D Operating Range 2-V to 5.5-V V_CC
D 3-State Outputs Directly Drive Bus Lines
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
description/ordering information
The ’AHC573 devices are octal transparent
D-type latches designed for 2-V to 5.5-V V_CC
operation.
When the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is
low, the Q outputs are latched at the logic levels
of the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
SN54AHC573 . . . J OR W PACKAGE
SN74AHC573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
GND 10
20 V_CC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 LE
SN54AHC573 . . . FK PACKAGE
(TOP VIEW)
3D
3 2 1 20 19
4
18
2Q
4D ₅
17 ^3Q
5D 6
16 4Q
6D 7
15 5Q
7D 8
14 6Q
9 10 11 12 13
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube
SN74AHC573N
SN74AHC573N
SOIC − DW
Tube
Tape and reel
SN74AHC573DW
SN74AHC573DWR
AHC573
−40°C to 85°C
SOP − NS
SSOP − DB
Tape and reel
Tape and reel
SN74AHC573NSR
SN74AHC573DBR
AHC573
HA573
TSSOP − PW
Tube
Tape and reel
SN74AHC573PW
SN74AHC573PWR
HA573
TVSOP − DGV
Tape and reel SN74AHC573DGVR
HA573
CDIP − J
Tube
SNJ54AHC573J
SNJ54AHC573J
−55°C to 125°C CFP − W
Tube
SNJ54AHC573W
SNJ54AHC573W
LCCC − FK
Tube
SNJ54AHC573FK
SNJ54AHC573FK
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2004, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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