SN54ACT574_07 Datasheet, PDF (1/15 Pages) Texas Instruments – OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54ACT574, SN74ACT574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS537D – OCTOBER 1995 – REVISED NOVEMBER 2002
D 4.5-V to 5.5-V V_CC Operation
D Inputs Accept Voltages to 5.5 V
D Max t_pd of 9 ns at 5 V
D Inputs Are TTL-Voltage Compatible
description/ordering information
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ’ACT574 devices are
D-type edge-triggered flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels set up at the data (D)
inputs.
SN54ACT574 . . . J OR W PACKAGE
SN74ACT574 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
GND 10
20 V_CC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 CLK
SN54ACT574 . . . FK PACKAGE
(TOP VIEW)
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
the increased drive provide the capability to drive
bus lines in a bus-organized system without need
for interface or pullup components.
3 2 1 20 19
3D 4
18 2Q
4D 5
17 3Q
5D 6
16 _4Q
6D ⁷
15 _5Q
7D ⁸
14 _6Q
9 10 11 12 13
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74ACT574N
SN74ACT574N
–40°C to 85°C
SOIC – DW
SOP – NS
Tube
Tape and reel
Tape and reel
SN74ACT574DW
SN74ACT574DWR
SN74ACT574NSR
ACT574
ACT574
SSOP – DB
Tape and reel SN74ACT574DBR
AD574
TSSOP – PW
Tape and reel SN74ACT574PWR
AD574
CDIP – J
Tube
SNJ54ACT574J
SNJ54ACT574J
–55°C to 125°C CFP – W
Tube
SNJ54ACT574W
SNJ54ACT574W
LCCC – FK
Tube
SNJ54ACT574FK
SNJ54ACT574FK
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright  2002, Texas Instruments Incorporated
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