SN54ACT374_02 Datasheet, PDF (1/14 Pages) Texas Instruments – OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54ACT374, SN74ACT374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS539F – OCTOBER 1995 – REVISED NOVEMBER 2002
D 4.5-V to 5.5-V V_CC Operation
D Inputs Accept Voltages to 5.5 V
D Max t_pd of 10 ns at 5 V
D Inputs Are TTL-Voltage Compatible
description/ordering information
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ’ACT374 devices are
D-type edge-triggered flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels set up at the data (D)
inputs.
SN54ACT374 . . . J OR W PACKAGE
SN74ACT374 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
SN54ACT374 . . . FK PACKAGE
(TOP VIEW)
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
the increased drive provide the capability to drive
bus lines in bus-organized systems without need
for interface or pullup components.
3 2 1 20 19
2D ₄
18 ^8D
2Q 5
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 13
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74ACT374N
SN74ACT374N
–40°C to 85°C
SOIC – DW
SOP – NS
Tube
Tape and reel
Tape and reel
SN74ACT374DW
SN74ACT374DWR
SN74ACT374NSR
ACT374
ACT374
SSOP – DB
Tape and reel SN74ACT374DBR
AD374
TSSOP – PW
Tape and reel SN74ACT374PWR
AD374
CDIP – J
Tube
SNJ54ACT374J
SNJ54ACT374J
–55°C to 125°C CFP – W
Tube
SNJ54ACT374W
SNJ54ACT374W
LCCC – FK
Tube
SNJ54ACT374FK
SNJ54ACT374FK
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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