SN54ACT3641 Datasheet, PDF (1/26 Pages) Texas Instruments – 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

D Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
D Clocked FIFO Buffering Data From Port A
to Port B
D Memory Size: 1024 × 36
D Synchronous Read-Retransmit Capability
D Mailbox Register in Each Direction
D Programmable Almost-Full and
Almost-Empty Flags
D Microprocessor Interface Control Logic
D Input-Ready and Almost-Full Flags
Synchronized by CLKA
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
D Output-Ready and Almost-Empty Flags
Synchronized by CLKB
D Low-Power 0.8 µm Advanced CMOS
Technology
D Supports Clock Frequencies up to 50 MHz
D Fast Access Times of 15 ns
D Released as DSCC SMD (Standard
Microcircuit Drawing) 5962-9560801QYA
and 5962-9560801NXD
D Package Options include 132-Pin Ceramic
Quad Flat (HFP) and 120-Pin Plastic Quad
Flat (PCB) Packages
description
The SN54ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies
up to 50 MHz and has read access times as fast as 15 ns. The 1024 × 36 dual-port SRAM FIFO buffers data
from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be
accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost
full and almost empty) to indicate when a selected number of words is stored in memory. Communication
between each port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal
when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths.
Expansion is also possible in word depth.
The SN54ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. The
output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset
values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input.
The SN54ACT3641 is characterized for operation over the full military temperature range of – 55°C to 125°C.
For more information on this device family, see the following application reports:
• FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering
(literature number SCAA009)
• FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature number SCAA007)
• Metastability Performance of Clocked FIFOs (literature number SCZA004)
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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