SN54ACT3632 Datasheet, PDF (1/25 Pages) Texas Instruments – 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SN54ACT3632
512 × 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998
D Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
D Two Independent 512 × 36 Clocked FIFOs
Buffering Data in Opposite Directions
D Mailbox-Bypass Register for Each FIFO
D Programmable Almost-Full and
Almost-Empty Flags
D Microprocessor Interface Control Logic
D IRA, ORA, AEA, and AFA Flags
Synchronized by CLKA
D Released as DESC SMD (Standard
Microcircuit Drawing) 5962-9562801QYA
D IRB, ORB, AEB, and AFB Flags
Synchronized by CLKB
D Low-Power 0.8-µm Advanced CMOS
Technology
D Supports Clock Frequencies up to 50 MHz
D Fast Access Times of 13 ns
D Packaged in 132-Pin Ceramic Quad Flat
Package
description
The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock
frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port
SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full
conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of
words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox
registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can
be used in parallel to create wider data paths.
The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The input-ready (IRA, IRB) flag and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the
port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA, AEB) flag
of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the
almost-full and almost-empty flags of both FIFOs can be programmed from port A.
The SN54ACT3632 is characterized for operation over the full military temperature range of –55°C to 125°C.
For more information on this device family, see the following application reports:
D FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature number SCAA007)
D Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors (literature number SCAA005)
D Metastability Performance of Clocked FIFOs (literature number SCZA004)
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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