SN54AC564_06 Datasheet, PDF (1/13 Pages) Texas Instruments – OCTAL D-TYPE EDGE-TRIGGERDE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54AC564, SN74AC564
OCTAL DĆTYPE EDGEĆTRIGGERED FLIPĆFLOPS
WITH 3ĆSTATE OUTPUTS
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003
D 2-V to 6-V V_CC Operation
D Inputs Accept Voltages to 6 V
D Max t_pd of 9 ns at 5 V
D 3-State Inverting Outputs Drive Bus Lines
Directly
D Full Parallel Access for Loading
D Flow-Through Architecture to Optimize
PCB Layout
description/ordering information
The ’AC564 devices are octal D-type
edge-triggered flip-flops that feature inverting
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
SN54AC564 . . . J OR W PACKAGE
SN74AC564 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D ⁹
GND ¹⁰
20 V_CC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 _8Q
11 _CLK
SN54AC564 . . . FK PACKAGE
(TOP VIEW)
On the positive transition of the clock (CLK) input,
the Q outputs are set to the inverse logic levels set
up at the data (D) inputs.
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
3 2 1 20 19
3D 4
18 2Q
4D 5
17 3Q
5D 6
16 4Q
6D 7
15 5Q
7D 8
14 6Q
9 10 11 12 13
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
SOIC − DW
Tube
Tube
Tape and reel
SN74AC564N
SN74AC564DW
SN74AC564DWR
SN74AC564N
AC564
−40°C to 85°C
SOP − NS
SSOP − DB
Tape and reel
Tape and reel
SN74AC564NSR
SN74AC564DBR
AC564
AC564
TSSOP − PW
Tube
Tape and reel
SN74AC564PW
SN74AC564PWR
AC564
CDIP − J
Tube
SNJ54AC564J
SNJ54AC564J
−55°C to 125°C CFP − W
Tube
SNJ54AC564W
SNJ54AC564W
LCCC − FK
Tube
SNJ54AC564FK
SNJ54AC564FK
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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