SN54ABTH16823 Datasheet, PDF (1/9 Pages) Texas Instruments – 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MAY 1997
D Members of the Texas Instruments
Widebus™ Family
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Typical V_OLP (Output Ground Bounce) < 1 V
at V_CC = 5 V, T_A = 25°C
D High-Impedance State During Power Up
and Power Down
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D High-Drive Outputs (–32-mA I_OH, 64-mA I_OL)
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
These 18-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
SN54ABTH16823 . . . WD PACKAGE
SN74ABTH16823 . . . DGG OR DL PACKAGE
(TOP VIEW)
1CLR 1
1OE 2
1Q1 3
GND 4
1Q2 5
1Q3 6
V_CC 7
1Q4 8
1Q5 9
1Q6 10
GND 11
1Q7 12
1Q8 13
1Q9 14
2Q1 15
2Q2 16
2Q3 17
GND 18
2Q4 19
2Q5 20
2Q6 21
V_CC 22
2Q7 23
2Q8 24
GND 25
2Q9 26
2OE 27
2CLR 28
56 1CLK
55 1CLKEN
54 1D1
53 GND
52 1D2
51 1D3
50 V_CC
49 1D4
48 1D5
47 1D6
46 GND
45 1D7
44 1D8
43 1D9
42 2D1
41 2D2
40 2D3
39 GND
38 2D4
37 2D5
36 2D6
35 V_CC
34 2D7
33 2D8
32 GND
31 2D9
30 2CLKEN
29 2CLK
The ’ABTH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input
low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the
clock buffer, latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently
of the clock.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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