SN54ABT833 Datasheet, PDF (1/9 Pages) Texas Instruments – 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical V_OLP (Output Ground Bounce) < 1 V
at V_CC = 5 V, T_A = 25°C
D High-Drive Outputs (–32-mA I_OH,
64-mA I_OL )
D Parity Error Flag With Parity
Generator/Checker
D Register for Storage of the Parity Error Flag
D Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
description
The ’ABT833 8-bit to 9-bit parity transceivers are
designed for communication between data buses.
When data is transmitted from the A bus to the
B bus, a parity bit is generated. When data is
transmitted from the B bus to the A bus with its
corresponding parity bit, the open-collector
parity-error (ERR) output indicates whether or not
an error in the B data has occurred. The
output-enable (OEA and OEB) inputs can be used
to disable the device so that the buses are
effectively isolated. The ’ABT833 provide true
data at their outputs.
A 9-bit parity generator/checker generates a
parity-odd (PARITY) output and monitors the
parity of the I/O ports with the ERR flag. ERR is
clocked into the register on the rising edge of the
clock (CLK) input. The error flag register is cleared
with a low pulse on the clear (CLR) input. When
both OEA and OEB are low, data is transferred
from the A bus to the B bus and inverted parity is
generated. Inverted parity is a forced error
condition that gives the designer more system
diagnostic capability.
SN54ABT833, SN74ABT833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997
SN54ABT833 . . . JT PACKAGE
SN74ABT833 . . . DW OR NT PACKAGE
(TOP VIEW)
OEA 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
ERR 10
CLR 11
GND 12
24 V_CC
23 B1
22 B2
21 B3
20 B4
19 B5
18 B6
17 B7
16 B8
15 PARITY
14 OEB
13 CLK
SN54ABT833 . . . FK PACKAGE
(TOP VIEW)
4 3 2 1 28 27 26
A3 5
25 B3
A4 6
24 B4
A5 7
23 B5
NC 8
22 NC
A6 9
21 B6
A7 10
20 B7
A8 11
19 B8
12 13 14 15 16 17 18
NC – No internal connection
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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