SN54ABT18652 Datasheet, PDF (1/11 Pages) Texas Instruments – SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS

• Members of the Texas Instruments
SCOPE ™ Family of Testability Products
• Members of the Texas Instruments
Widebus ™ Family
• Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
• Include D-Type Flip-Flops and Control
Circuitry to Provide Multiplexed
Transmission of Stored and Real-Time Data
• Two Boundary-Scan Cells per I/O for
Greater Flexibility
• State-of-the-Art EPIC-ΙΙB ™ BiCMOS Design
Significantly Reduces Power Dissipation
SN54ABT18652, SN74ABT18652
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992
• SCOPE ™ Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, and
P1149.1A CLAMP and HIGHZ
– Parallel Signature Analysis at Inputs With
Masking Option
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
• Packaged in 64-Pin Plastic Shrink Quad Flat
Pack (PM) and 68-Pin Ceramic Quad Flat
Pack (HV)
SN54ABT18652 . . . HV PACKAGE
(TOP VIEW)
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
NC
V_CC
2A1
2A2
2A3
GND
2A4
2A5
2A6
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
1
51
2
50
3
49
4
48
5
47
6
46
7
45
8
44
9
43
10
42
11
41
12
40
13
39
14
38
15
37
16
36
17
35
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
1B4
1B5
1B6
GND
1B7
1B8
1B9
V_CC
NC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
NC – No internal connection
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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Copyright © 1992, Texas Instruments Incorporated
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