SN54ABT18640 Datasheet, PDF (1/30 Pages) Texas Instruments – SCAN TEST DEVICES WITH 18-BIT INVERTING BUS TRANSCEIVERS

SN54ABT18640, SN74ABT18640
SCAN TEST DEVICES
WITH 18-BIT INVERTING BUS TRANSCEIVERS
SCBS267C – FEBRUARY 1994 – REVISED JULY 1996
D Members of the Texas Instruments
SCOPE ™ Family of Testability Products
D Members of the Texas Instruments
Widebus™ Family
D Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
D SCOPE ™ Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D Packaged in Plastic Shrink Small-Outline
(DL) and Thin Shrink Small-Outline (DGG)
Packages and 380-mil Fine-Pitch Ceramic
Flat (WD) Packages
description
The ’ABT18640 scan test devices with 18-bit
inverting bus transceivers are members of the
Texas Instruments SCOPE™ testability
integrated-circuit family. This family of devices
supports IEEE Standard 1149.1-1990 boundary
scan to facilitate testing of complex circuit-board
assemblies. Scan access to the test circuitry is
accomplished via the 4-wire test access port
(TAP) interface.
SN54ABT18640 . . . WD PACKAGE
SN74ABT18640 . . . DGG OR DL PACKAGE
(TOP VIEW)
1DIR 1
1B1 2
1B2 3
GND 4
1B3 5
1B4 6
V_CC 7
1B5 8
1B6 9
1B7 10
GND 11
1B8 12
1B9 13
2B1 14
2B2 15
2B3 16
2B4 17
GND 18
2B5 19
2B6 20
2B7 21
V_CC 22
2B8 23
2B9 24
GND 25
2DIR 26
TDO 27
TMS 28
56 1OE
55 1A1
54 1A2
53 GND
52 1A3
51 1A4
50 V_CC
49 1A5
48 1A6
47 1A7
46 GND
45 1A8
44 1A9
43 2A1
42 2A2
41 2A3
40 2A4
39 GND
38 2A5
37 2A6
36 2A7
35 V_CC
34 2A8
33 2A9
32 GND
31 2OE
30 TDI
29 TCK
In the normal mode, these devices are 18-bit inverting bus transceivers. They can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP
in the normal mode does not affect the functional operation of the SCOPE™ bus transceivers.
Data flow is controlled by the direction-control (DIR) and output-enable (OE) inputs. Data transmission is
allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE can
be used to disable the device so that the buses are effectively isolated.
In the test mode, the normal operation of the SCOPE™ bus transceivers is inhibited and the test circuitry is
enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform
boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE, Widebus, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1