SN54ABT16841 Datasheet, PDF (1/7 Pages) Texas Instruments – 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
D Members of the Texas Instruments
Widebus ™ Family
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 5 V, T_A = 25°C
D High-Impedance State During Power Up
and Power Down
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D High-Drive Outputs (–32-mA I_OH, 64-mA I_OL)
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
description
These 20-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
SN54ABT16841 . . . WD PACKAGE
SN74ABT16841 . . . DL PACKAGE
(TOP VIEW)
1OE ¹
1Q1 ²
1Q2 ³
GND ⁴
1Q3 ⁵
1Q4 ⁶
V_CC ⁷
1Q5 ⁸
1Q6 ⁹
1Q7 ¹⁰
GND ¹¹
1Q8 ¹²
1Q9 ¹³
1Q10 ¹⁴
2Q1 ¹⁵
2Q2 ¹⁶
2Q3 ¹⁷
GND ¹⁸
2Q4 ¹⁹
2Q5 ²⁰
2Q6 ²¹
V_CC ²²
2Q7 ²³
2Q8 ²⁴
GND ²⁵
2Q9 ²⁶
2Q10 ²⁷
2OE ²⁸
56 _1LE
55 _1D1
54 _1D2
53 _GND
52 _1D3
51 _1D4
50 _VCC
49 _1D5
48 _1D6
47 _1D7
46 _GND
45 _1D8
44 _1D9
43 _1D10
42 _2D1
41 _2D2
40 _2D3
39 _GND
38 _2D4
37 _2D5
36 _2D6
35 _VCC
34 _2D7
33 _2D8
32 _GND
31 _2D9
30 _2D10
29 _2LE
The ’ABT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 transparent D-type latches provide
true data at the outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding
10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D
inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
The output-enable input does not affect the internal operation of the latches. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
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