SN54ABT16373 Datasheet, PDF (1/8 Pages) Texas Instruments – 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

• Members of the Texas Instruments
Widebus ™ Family
• State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
• Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 5 V, T_A = 25°C
• Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
• Flow-Through Architecture Optimizes
PCB Layout
• High-Drive Outputs (– 32-mA I_OH,
64-mA I_OL)
• Packaged in Plastic 300-mil Shrink
Small-Outline Packages and 380-mil
Fine-Pitch Ceramic Flat Packages Using
25-mil Center-to-Center Spacings
description
The 4ABT16373 is a 16-bit transparent D-type
latch with 3-state outputs designed specifically for
driving highly capacitive or relatively
low-impedance loads. It is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
SN54ABT16373, SN74ABT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992
SN54ABT16373 . . . WD PACKAGE
SN74ABT16373 . . . DL PACKAGE
(TOP VIEW)
1OE 1
1Q1 2
1Q2 3
GND 4
1Q3 5
1Q4 6
V_CC 7
1Q5 8
1Q6 9
GND 10
1Q7 11
1Q8 12
2Q1 13
2Q2 14
GND 15
2Q3 16
2Q4 17
V_CC 18
2Q5 19
2Q6 20
GND 21
2Q7 22
2Q8 23
2OE 24
48 1LE
47 1D1
46 1D2
45 GND
44 1D3
43 1D4
42 V_CC
41 1D5
40 1D6
39 GND
38 1D7
37 1D8
36 2D1
35 2D2
34 GND
33 2D3
32 2D4
31 V_CC
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2LE
The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the
D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components
The output enable (OE) does not affect internal operations of the latch. Old data can be retained or new data
can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT16373 is available in TI’s shrink small-outline package (DL), which provides twice the I/O pin
count and functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ABT16373 is characterized for operation over the full military temperature range of – 55°C to 125°C.
The SN74ABT16373 is characterized for operation from – 40°C to 85°C.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright © 1992, Texas Instruments Incorporated
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