SM320C6201 Datasheet, PDF (1/73 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
D Highest Performance Fixed-Point Digital
Signal Processor (DSP) SM320C6201
– 6.67-ns Instruction Cycle Time
– 150-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 1 200 MIPS
D Highest Performance Fixed-Point Digital
Signal Processor (DSP) SMJ320C6201B
– 6.67-ns Instruction Cycle Time
– 150-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 1 200 MIPS
D VelociTI™ Advanced Very Long Instruction
Word (VLIW) ’C6200 CPU Core
– Eight Independent Functional Units:
– Six ALUs (32-/40-Bit)
– Two 16-Bit Multipliers (32-Bit Results)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
D Instruction Set Features
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 32-Bit Address Range
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
D 1M-Bit On-Chip SRAM
– 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
– 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as a Single Block
(’6201)
– 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as Two Blocks for
Improved Concurrency (’6201B)
D 32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
D Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
with an Auxiliary Channel
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
GLE and GLP PACKAGES
( BOTTOM VIEW )
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 3 5 7 9 11 13 15 17 19 21
2 4 6 8 10 12 14 16 18 20
D 16-Bit Host-Port Interface (HPI)
– Access to Entire Memory Map
D Two Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial Peripheral Interface (SPI)
Compatible (Motorola™)
D Two 32-Bit General-Purpose Timers
D Flexible Phase-Locked Loop (PLL) Clock
Generator
D IEEE-1149.1 (JTAG^†) Boundary-Scan
Compatible
D 429-Pin BGA Package (GLE Suffix) (’6201)
D 429-Pin BGA Package (GLP Suffix) (’6201B)
D CMOS Technology
– 0.25-µm/5-Level Metal Process (’6201)
– 0.18-µm/5-Level Metal Process (’6201B)
D 3.3-V I/Os, 2.5-V Internal (’6201)
D 3.3-V I/Os, 1.8-V Internal (’6201B)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
† _{IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.}
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright © 1998, Texas Instruments Incorporated
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